Job Description

Roles & Responsibilities

We are seeking a highly skilled Digital Verification Engineer to lead the verification strategy and execution for complex designs. You will drive methodology, architecture, and signoff quality, working closely with system, digital design, architecture, and physical implementation teams. This is a hands-on leadership role combining deep technical expertise with mentorship and cross-functional influence.

Key Responsibilities

• Define and own end-to-end verification strategy for IPs and complex SoCs
• Architect and deploy scalable UVM-based verification environments
• Lead block-level, subsystem, and full-chip verification closure
• Drive coverage closure (functional + code + assertion)
• Best practices in: Constrained random verification, Assertions, Regression management and debug efficiently
• Drives regression automation (CI/CD, regression infrastructure, dashboards)

Required skills

• BS or MS in Electrical and Computer Engineering with 10+ years of experience in digital verification
• Proven track record in SoC level verification and signoff
• Experience building reusable and scalable verification environments
• Proficiency in System verilog, UVM methodology, and Assertions (SVA)
• Strong experience in simulations and debug tools (e.g. vcs, verdi, spyglass)
• Deep understanding in clock/reset domain crossing
• knowledge of scripting (python, perl, TCL) for automation
• Experience with formal verification tools and methodologies
• Preferred knowledge in low-power verification (UPF/CPF is a plus)

Desired Candidate Profile

BS or MS in Electrical and Computer Engineering with 10+ years of experience in digital verification

Proven track record in SoC level verification and signoff

Experience building reusable and scalable verification environments

Proficiency in System verilog, UVM methodology, and Assertions (SVA)

Strong experience in simulations and debug tools (e.g. vcs, verdi, spyglass)

Deep understanding in clock/reset domain crossing

knowledge of scripting (python, perl, TCL) for automation

Experience with formal verification tools and methodologies

Preferred knowledge in low-power verification (UPF/CPF is a plus)