Job Description

Roles & Responsibilities

Responsible for micro-architecture specification and RTL design of modules in Verilog

• Responsible for project direction and planning, mentoring and technical guidance of the team.

• Lead development teams in the development of digital controllers through the full project lifecycle, including analysis, design, development, verification, testing and implementation.

• Leading verification team to develop advanced test plans.

• Hardware verification of the digital module using cutting edge FPGA kits.

• Provide technical leadership on one or more projects

• Solve complex problems which may be multidisciplinary or require an in-depth analysis of variable factors

• Defining project-specific best practices, and lead code reviews.

• Identifying opportunities for improving productivity and reducing errors.

• Communication of project status, risk and successes to internal and external stakeholders.

• Team planning and team member resource utilization.

Desired Candidate Profile

Essential Qualifications and Experience:

• Bachelor s degree of: Electronics Engineering.

• Years of experience in the same field: +7 Years of experience in VLSI Digital Design/Verification

• Strong knowledge of Verilog RTL design/simulation.

• Proficiency in ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.

• Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques

• Solid understanding of System Verilog, UVM, RTL/gate verification techniques

• Solid understanding of functional and code coverage metrics and closure

• Strong knowledge in shell/perl/python scripting languages.

Desirable Qualifications and Experience:

• Knowledge of high level synthesis techniques and C-simulation/validation

• Masters Degree is a plus.