Job Description

Roles & Responsibilities

Develop test plan from specification and architect system level verification environments. Develop and maintain UVM-based testbenches for block-level and subsystem-level verification Write constrained-random stimulus, scoreboards, monitors, and coverage models in SystemVerilog Contribute to regression infrastructure, continuous integration flows, and internal verification methodology Drive functional and code coverage closure; analyze coverage holes and add targeted tests Integrate and configure VIP (Verification IP) for standard protocols Support FPGA-based prototyping and pre-silicon bring-up with validation test suites Execute RTL/Gate level simulations and analyze results. Contribute to design/verification process automation.

Desired Candidate Profile

• Bachelor s degree of: Electronics/Computer Engineering.
• Years of experience in the same field: 0-3 Years of experience in developing SV-based verification environments.
• Strong knowledge of Verilog, System Verilog, and object-oriented programming languages.
• Strong proficiency in UVM methodology
• Solid understanding of functional and code coverage metrics and closure
• English Language Proficiency: Fluency
• Computer skills required: Unix/Linux operating system.

Desirable Qualifications and Experience:

• Familiarity with RTL design, synthesis, and CDC analysis.
• Working knowledge of shell, Perl, and TCL scripting.