Job Description

Roles & Responsibilities

Responsibilities:

• Perform moderately complex development activities, including the design, implementation, maintenance, testing, and documentation of software modules and subsystems for physical design, place-and-route, and 3D packaging.
• Develop scalable and customized solutions, streamline and automate workflows, and deploy robust production code using Python, Tcl/Tk, Bash, and other scripting tools and languages focused on physical implementation and packaging.
• Apply strong problem-solving skills to identify complex physical design, packaging, tool, or workflow issues and facilitate their resolution.
• Improve physical design and packaging flows and methodologies for advanced technology nodes, with a focus on performance, power, and area (PPA) optimization.
• Support the integration and enhancement of flows related to floorplanning, placement, routing, power integrity, signal integrity, and physical verification for 3D ICs and advanced packaging.
• Collaborate with CAD, 3D/2.5D packaging, and physical implementation teams to address workflow requirements and drive innovation in place-and-route and packaging solutions.
• Contribute to the development and integration of 3DBlox-, 3DStack-, and industry standards-based solutions relevant to 3D IC/3DStack architectures and advanced packaging.
• Manage design data and EDA infrastructure related to physical design and packaging, including tool installation and maintenance, server environment setup (Linux/Windows), resource monitoring, and troubleshooting.

Required Skills:

• Bachelor s degree with 4+ years of experience, or a Master s degree with 2+ years of experience, in Computer Science, Computer Engineering, Electrical Engineering, or a closely related technical field.
• Strong scripting skills in Python, Tcl/Tk, and Shell/Bash.
• Strong understanding and hands-on experience with software data structures and software development in Windows and Linux environments.
• Prior experience with flow managers and Makefiles for building complex design structures and workflows.
• Proficiency in design data management and EDA infrastructure, including organizing large-scale design data, installing and upgrading EDA tools, and managing server environments.
• Deep understanding of ASIC physical design methodologies, from RTL synthesis through physical implementation (floorplanning, placement, routing, CTS, timing closure, and physical verification), including expertise in the netlist-to-GDS flow.
• Familiarity with version control systems (e.g., Git) and software development methodologies (e.g., Agile and Scrum).
• Ability to work both independently and collaboratively within a team with minimal supervision.
• Advanced English speaking and writing skills for effective communication within global teams.

Preferred Skills:

• Hands-on experience with industry-leading place-and-route tools (e.g., Cadence Innovus, Synopsys Fusion Compiler/ICC2, Siemens Aprisa) and physical verification tools (e.g., Siemens Calibre DRC, LVS, and PEX).
• Familiarity with package design tools (e.g., Cadence APD/SiP and Siemens Xpedition) and package/interposer planning solutions (e.g., Siemens Innovator 3D IC, Cadence Integrity/Innovus, and Synopsys 3DIC Compiler).
• Experience with 3D IC/3DStack solutions and related physical implementation challenges.
• Familiarity with IC analysis tools such as Siemens HyperLynx, Ansys HFSS and RedHawk, Cadence Voltus, or Synopsys PrimeTime for signal and power integrity analysis in physical design.
• Knowledge of advanced process nodes (e.g., FinFET technologies) and their impact on physical design.

Desired Candidate Profile

We are looking for a strong>Software Engineer /strong>to join our strong>CES-3DIC/strong> team in Cairo, Egypt. As a Software Engineer, you will contribute to the development of innovative software products and comprehensive workflow solutions for advanced 2.5D and 3D System-in-Package (SiP) designs. Your work will involve integrating Siemens industry-leading EDA and MCAD tools to facilitate architectural planning, physical design and verification, multi-die analysis (electrical, thermal, and mechanical stress), and manufacturing test, making a significant impact on the future of chip design.