Job Description

Roles & Responsibilities

Responsible for micro-architecture specification and RTL design of modules in Verilog Responsible for project direction and planning, mentoring and technical guidance of the team. Lead development teams in the development of digital controllers through the full project lifecycle, including analysis, design, development, verification, testing and implementation. Leading verification team to develop advanced test plans. Hardware verification of the digital module using cutting edge FPGA kits. Provide technical leadership on one or more projects Solve complex problems which may be multidisciplinary or require an in-depth analysis of variable factors Defining project-specific best practices, and lead code reviews. Identifying opportunities for improving productivity and reducing errors. Own delivery schedules, resource planning, and risk mitigation across concurrent projects Engage with customers and partners on IP deliverables, verification collateral, and integration support Represent the team in program reviews, milestone sign-offs, and customer-facing discussions Foster a culture of technical excellence, peer review, knowledge sharing, and continuous improvement Drive team motivation through clear vision-setting, timely recognition of achievements, and visible support during critical project phases

Desired Candidate Profile

• Bachelor s degree of: Electronics/Computer Engineering.
• Years of experience in the same field: 12+ Years of experience in VLSI Digital Design/Verification, with 3-5+ years in a people management or technical lead role
• Proven track record of taking IPs from spec to silicon-proven delivery
• Strong knowledge of Verilog RTL design/simulation.
• Proficiency in ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
• Strong knowledge of clock domain crossing (CDC) and reset domain crossing (RDC) techniques
• Experience with System Verilog, UVM, RTL/gate verification techniques
• Solid understanding of functional and code coverage metrics and closure
• Strong knowledge of Python/Perl/TCL/Shell scripting languages
• Experience working with global teams
• Knowledge of high level synthesis techniques and C-simulation/validation
• Masters Degree is a plus.