We're hiring a Senior Verification Engineer to lead functional verification on customer ASIC projects. You'll architect testbenches in proprietary and open-source verification stacks, drive coverage closure, and serve as the quality gate for our deliverables. This is a high-impact role on a small senior team.
Desired Candidate Profile
- 6+ years functional verification experience with production-quality bar
- Deep UVM and SystemVerilog assertions expertise
- Production experience with proprietary verification tools (Synopsys VCS, Cadence Xcelium, or Siemens Questa)
- Coverage methodology (functional + code) and coverage closure experience
- Bug tracking and verification reporting discipline
- BSc/MSc in Electrical Engineering, Computer Engineering, or related field