We're hiring a Senior Digital Design Engineer to own digital design holistically on signed and pipeline ASIC contracts. This isn't a pure RTL coder role you'll write production SystemVerilog, author timing constraints (SDC), design with power intent (UPF) in mind, and structure your RTL for testability (DFT-aware). You'll partner with verification, PnR, and our partner specialists, and represent NC technically in customer design reviews.
Desired Candidate Profile
- 6+ years digital design experience with at least one sub-90nm tape-out shipped
- Strong SystemVerilog and synthesis fluency
- Production SDC authoring experience clocks, IO timing, exceptions, MMMC sign-off setup
- UPF authoring experience for multi-Vt and power-gated designs
- DFT awareness write RTL that synthesizes cleanly for scan and is testable
- Production experience with proprietary flows (Synopsys VCS / Cadence Xcelium / Siemens Questa for verification; Design Compiler / Genus for synthesis)
- Solid grounding in clock/reset architecture and clock domain crossing methodology
- Comfortable working in customer-facing engineering reviews
- BSc/MSc in Electrical Engineering, Computer Engineering, or related field